/* * LTX971A PHY transceiver registers. * * Copyright (C) Elvees (www.multicore.ru) * * This file is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. * * You can redistribute this file and/or modify it under the terms of the GNU * General Public License (GPL) as published by the Free Software Foundation; * either version 2 of the License, or (at your discretion) any later version. * See the accompanying file "COPYING.txt" for more details. * */ #ifndef LTX971A_H #define LTX971A_H #define PHY_CTL 0 /* Basic Control */ #define PHY_STS 1 /* Basic Status */ #define PHY_ID1 2 /* PHY Identifier I */ #define PHY_ID2 3 /* PHY Identifier II */ #define PHY_ADVRT 4 /* Auto-Negotiation Advertisement */ #define PHY_RMT_ADVRT 5 /* Auto-Negotiation Link Partner Ability */ #define PHY_ANE 6 /* Auto-Negotiation Expansion */ #define PHY_ANNPTX 7 /* Auto-Negotiation Next Page Transmit register */ #define PHY_LPNPRX 8 /* Auto-Negotiation Link Partner Next Page Receive register */ #define PHY_PCFG 16 /* Port Configuration Register */ #define PHY_STS2 17 /* Status Register #2 */ #define PHY_IER 18 /* Interrupt Enable Register */ #define PHY_INTSTS 19 /* Interrupt Status Register */ #define PHY_LEDCFG 20 /* LED Configuration Register */ #define PHY_DCFG 26 /* Digital Config Register */ #define PHY_TXCTL 30 /* Transmit Control Register */ /* * Basic Control Register 0x00 */ #define PHY_CTL_COLTST 0x0080 /* collision test enable */ #define PHY_CTL_DPLX 0x0100 /* full duplex */ #define PHY_CTL_ANEG_RST 0x0200 /* write 1 to restart autoneg */ #define PHY_CTL_MII_DIS 0x0400 /* MII interface disable */ #define PHY_CTL_PDN 0x0800 /* powerdown enable */ #define PHY_CTL_ANEG_EN 0x1000 /* auto-negotiation enable */ #define PHY_CTL_SPEED_100 0x2000 /* select 100 Mbps speed */ #define PHY_CTL_LPBK 0x4000 /* loopback enable */ #define PHY_CTL_RST 0x8000 /* reset, bit self cleared */ #define PHY_CTL_BITS "\20\10coltst"\ "\11dplx\12aneg-rst\13mii-dis\14pdn\15aneg-en\16speed100\17lpbk\20rst" /* * Basic Status register 0x01 */ #define PHY_STS_EXREG 0x0001 /* extended regs enabled */ #define PHY_STS_JAB 0x0002 /* jabber detected */ #define PHY_STS_LINK 0x0004 /* link valid */ #define PHY_STS_CAP_ANEG 0x0008 /* auto-negotiation available */ #define PHY_STS_REM_FLT 0x0010 /* remote fault detected */ #define PHY_STS_ANEG_CMPL 0x0020 /* auto-negotiation complete */ #define PHY_PRE_SPPR 0x0040 /* MF Preamble Suppression */ #define PHY_EXT_STATUS 0x0100 /* extended status in register 15 */ #define PHY_STS_CAP_10_HDX 0x0800 /* 10Base-T half duplex */ #define PHY_STS_CAP_10_FDX 0x1000 /* 10Base-T full duplex */ #define PHY_STS_CAP_100X_HDX 0x2000 /* can do 100Base-TX half duplex */ #define PHY_STS_CAP_100X_FDX 0x4000 /* can do 100Base-X full duplex */ #define PHY_STS_CAP_100T4_FDX 0x8000 /* can do 100Base-T4 */ #define PHY_STS_BITS "\20"\ "\1exreg\2jab\3link\4cap-aneg\5rem-flt\6aneg-cmpl\9ext-stat"\ "\10hdx100T2\11fdx100T2\12hdx10T\13fdx10T\14hdx100TX\15fdx100TX\16T4-100" /* * ID1-ID2 registers */ #define PHY_ID1_NUMB 0x0013 #define PHY_ID_MASK 0xfffffff0 #define PHY_ID2_NUMB 0x001378E0 /* * Auto negotiation advertisement, * Auto negotiation remote end capability 0x04 */ #define PHY_ADVRT_CSMA 0x0001 /* capable of 802.3 CSMA operation */ #define PHY_ADVRT_ISLAN 0x0002 /* capable of IEEE 802.9 ISLAN-16T */ #define PHY_ADVRT_10 0x0020 /* can do 10Base-T */ #define PHY_ADVRT_10_FDX 0x0040 /* can do 10Base-T full duplex */ #define PHY_ADVRT_100 0x0080 /* can do 100Base-TX */ #define PHY_ADVRT_100_FDX 0x0100 /* can do 100Base-TX full duplex */ #define PHY_ADVRT_100_T4 0x0200 /* can do 100Base-T4 */ #define PHY_ADVRT_PAUSE 0x0400 /* pause function supported */ #define PHY_ADVRT_ASYMP 0x0800 /* Asymmetric Pause */ #define PHY_ADVRT_RF 0x2000 /* remote fault */ #define PHY_ADVRT_NXTPG 0x8000 /* Port has ability to send multiple pages */ #define PHY_ADVRT_BITS "\20"\ "\1csma\5t10\6fdx-t10\7tx100\8fdx-tx100\13rf" /* * Auto negotiation link partner ability register 0x05 */ #define PHY_ANLP_CSMA 0x0001 /* capable of 802.3 CSMA operation */ #define PHY_ANLP_ISLAN 0x0002 /* capable of IEEE 802.9 ISLAN-16T */ #define PHY_ANLP_10T 0x0020 /* capable 10BASE-T */ #define PHY_ANLP_10TFDX 0x0040 /* capable 10BASE-T full duplex */ #define PHY_ANLP_100TX 0x0080 /* capable 100BASE-TX */ #define PHY_ANLP_100TXFDX 0x0100 /* capable 100Base-TX full duplex */ #define PHY_ANLP_100T4 0x0200 /* capable 100Base-t4 */ #define PHY_ANLP_PAUSE 0x0400 /* Pause supported */ #define PHY_ANLP_ASPAUSE 0x0800 /* Link Partner is Pause capable */ #define PHY_ANLP_RFLT 0x2000 /* Remote fault */ #define PHY_ANLP_ACK 0x4000 /* Acknowledge */ #define PHY_ANLP_NP 0x8000 /* Next Page */ /* * Auto negotiation expansion register 0x06 */ #define PHY_ANEX_ANAB 0x0001 /* Link partner auto-negotiation able */ #define PHY_ANEX_PGRCV 0x0002 /* Page received */ #define PHY_ANEX_NPAB 0x0004 /* Next page able */ #define PHY_ANEX_LPNPAB 0x0008 /* Link partner next page able */ #define PHY_ANEX_PDF 0x0010 /* Parallel detection fault */ #define PHY_ANEX_BSPG 0x0020 /* Base page = true */ /* * Auto-Negotiation Next Page register 0x07 */ #define PHY_ANNPTX_T 0x0800 /* Toggle - Previous value of the transmitted Link Code Word equalled logic zero */ #define PHY_ANNPTX_ACK2 0x1000 /* Acknowledge 2 1 = Complies with message */ #define PHY_ANNPTX_MP 0x2000 /* Message Page */ #define PHY_ANNPTX_NP 0x8000 /* Next Page */ /* * Auto-Negotiation Link Partner Next Page Receive register 8 */ #define PHY_LPNPRX_T 0x0800 /* Toggle - Previous value of the transmitted Link Code Word equalled logic zero */ #define PHY_LPNPRX_ACK2 0x1000 /* Acknowledge 2 1 = Link Partner complies with the message */ #define PHY_LPNPRX_MP 0x2000 /* Message Page Page sent by the Link Partner is a Message Page */ #define PHY_LPNPRX_ACK 0x4000 /* Acknowledge */ #define PHY_LPNPRX_NP 0x8000 /* Next Page Link Partner has additional next pages to send */ /* * Port Configuration Register 16 */ #define PHY_PCFG_FIBSEL 0x0001 /* Fiber Select 1 = Select fiber mode */ #define PHY_PCFG_ALTNP 0x0002 /* Alternate NP feature */ #define PHY_PCFG_FLTCD_EN 0x0004 /* Fault Code Enable */ #define PHY_PCFG_SLP2 0x0008 /* Sleep Timer 2 sec */ #define PHY_PCFG_SLP1 0x0010 /* Sleep Timer 1.04 sec */ #define PHY_PCFG_SLPDEF 0x0000 /* Sleep Timer 3.04 sec */ #define PHY_PCFG_PRE_EN 0x0020 /* Preamble Enable */ #define PHY_PCFG_SLPMD 0x0040 /* Sleep Mode */ #define PHY_PCFG_CRS_SEL 0x0080 /* CRS Select (10BASE-T) */ #define PHY_PCFG_TPLPBK 0x0100 /* Disable TP loopback during half-duplex operation */ #define PHY_PCFG_SQE 0x0200 /* Enable Heart Beat (10BASE-T) */ #define PHY_PCFG_JABBR 0x0400 /* Disable Jabber Correction */ #define PHY_PCFG_BP_SCR 0x1000 /* Bypass Scrambler and Descrambler (100BASE-TX) */ #define PHY_PCFG_TX_DIS 0x2000 /* Disable Twisted Pair transmitter */ #define PHY_PCFG_FLNKP 0x4000 /* Force Link pass */ /* * Status Register #2 17 */ #define PHY_STS2_ERR 0x0008 /* 1 = Error Occurred (Remote Fault, X,Y, Z). */ #define PHY_STS2_PAUSE 0x0010 /* Device Pause capable */ #define PHY_STS2_PL_RV 0x0020 /* 1 = Polarity is reversed. */ #define PHY_STS2_AN_CMPL 0x0080 /* 1 = Auto-negotiation process completed */ #define PHY_STS2_AN 0x0100 /* LXT971A is in auto-negotiation mode */ #define PHY_STS2_FDPX 0x0200 /* 1 = Full-duplex. */ #define PHY_STS2_LINK 0x0400 /* Link is up */ #define PHY_STS2_COLL 0x0800 /* 1 = Collision is occurring */ #define PHY_STS2_RXS 0x1000 /* 1 = LXT971A is receiving a packet */ #define PHY_STS2_TXS 0x2000 /* 1 = LXT971A is transmitting a packet */ #define PHY_STS2_MODE 0x4000 /* 1 = LXT971A is operating in 100BASE-TX mode. */ /* * Interrupt enable register 18 */ #define PHY_IER_TINT 0x0001 /* Force interrupt on MDINT */ #define PHY_IER_INTEN 0x0002 /* Enable interrupts */ #define PHY_IER_LINKMSK 0x0010 /* Mask for Link Status Interrupt 1 = Enable event to cause interrupt */ #define PHY_IER_DUPLEXMSK 0x0020 /* Mask for Duplex Interrupt */ #define PHY_IER_SPEEDMSK 0x0040 /* Mask for Speed Interrupt */ #define PHY_IER_ANMSK 0x0080 /* Mask for Auto Negotiate Complete */ /* * Interrupt status register 19 */ #define PHY_INTSTS_MDINT 0x0004 /* 1 = MII interrupt pending */ #define PHY_INTSTS_LINKCHG 0x0010 /* 1 = A Link Change has occurred since last reading this register */ #define PHY_INTSTS_DPLXCHG 0x0020 /* 1 = A Duplex Change has occurred since last reading this register */ #define PHY_INTSTS_SPDCHG 0x0040 /* 1 = A Speed Change has occurred since last reading this register */ #define PHY_INTSTS_ANDONE 0X0080 /* Auto-negotiation has completed */ /* * LED Configuration Register 20 */ #define PHY_LEDCFG_PULSE_STR 0x0002 /* 1 = Enable pulse stretching of all LEDs */ #define PHY_LEDCFG_FREQ30 0x0000 /* Stretch LED events to 30 ms. */ #define PHY_LEDCFG_FREQ60 0x0004 /* Stretch LED events to 60 ms. */ #define PHY_LEDCFG_FREQ100 0x0008 /* Stretch LED events to 100 ms. */ #define PHY_LEDCFG_3_SPD 0x0000 /* LED3 Display Speed Status */ #define PHY_LEDCFG_3_TXS 0x0010 /* LED3 Display Transmit Status */ #define PHY_LEDCFG_3_RXS 0x0020 /* LED3 Display Receive Status */ #define PHY_LEDCFG_3_CLS 0x0030 /* LED3 Display Collision Status */ #define PHY_LEDCFG_3_LNS 0x0040 /* LED3 Display Link Status */ #define PHY_LEDCFG_3_DPS 0x0050 /* LED3 Display Duplex Status */ #define PHY_LEDCFG_3_RTA 0x0070 /* LED3 Display Receive or Transmit Activity */ #define PHY_LEDCFG_3_LON 0x0080 /* LED3 Test mode- turn LED on */ #define PHY_LEDCFG_3_LOFF 0x0090 /* LED3 Test mode- turn LED off */ #define PHY_LEDCFG_3_BF 0x00A0 /* LED3 Test mode- blink LED fast */ #define PHY_LEDCFG_3_BS 0x00B0 /* LED3 Test mode- blink LED slow */ #define PHY_LEDCFG_3_LRS 0x00C0 /* LED3 Display Link and Receive Status combined */ #define PHY_LEDCFG_3_LAS 0x00D0 /* LED3 Display Link and Activity Status combined */ #define PHY_LEDCFG_3_DCS 0x00E0 /* LED3 Display Duplex and Collision Status combined */ #define PHY_LEDCFG_2_SPD 0x0000 /* LED2 Display Speed Status */ #define PHY_LEDCFG_2_TXS 0x0100 /* LED2 Display Transmit Status */ #define PHY_LEDCFG_2_RXS 0x0200 /* LED2 Display Receive Status */ #define PHY_LEDCFG_2_CLS 0x0300 /* LED2 Display Collision Status */ #define PHY_LEDCFG_2_LNS 0x0400 /* LED2 Display Link Status */ #define PHY_LEDCFG_2_DPS 0x0500 /* LED2 Display Duplex Status */ #define PHY_LEDCFG_2_RTA 0x0700 /* LED2 Display Receive or Transmit Activity */ #define PHY_LEDCFG_2_LON 0x0800 /* LED2 Test mode- turn LED on */ #define PHY_LEDCFG_2_LOFF 0x0900 /* LED2 Test mode- turn LED off */ #define PHY_LEDCFG_2_BF 0x0A00 /* LED2 Test mode- blink LED fast */ #define PHY_LEDCFG_2_BS 0x0B00 /* LED2 Test mode- blink LED slow */ #define PHY_LEDCFG_2_LRS 0x0C00 /* LED2 Display Link and Receive Status combined */ #define PHY_LEDCFG_2_LAS 0x0D00 /* LED2 Display Link and Activity Status combined */ #define PHY_LEDCFG_2_DCS 0x0E00 /* LED2 Display Duplex and Collision Status combined */ #define PHY_LEDCFG_1_SPD 0x0000 /* LED1 Display Speed Status */ #define PHY_LEDCFG_1_TXS 0x1000 /* LED1 Display Transmit Status */ #define PHY_LEDCFG_1_RXS 0x2000 /* LED1 Display Receive Status */ #define PHY_LEDCFG_1_CLS 0x3000 /* LED1 Display Collision Status */ #define PHY_LEDCFG_1_LNS 0x4000 /* LED1 Display Link Status */ #define PHY_LEDCFG_1_DPS 0x5000 /* LED1 Display Duplex Status */ #define PHY_LEDCFG_1_RTA 0x7000 /* LED1 Display Receive or Transmit Activity */ #define PHY_LEDCFG_1_LON 0x8000 /* LED1 Test mode- turn LED on */ #define PHY_LEDCFG_1_LOFF 0x9000 /* LED1 Test mode- turn LED off */ #define PHY_LEDCFG_1_BF 0xA000 /* LED1 Test mode- blink LED fast */ #define PHY_LEDCFG_1_BS 0xB000 /* LED1 Test mode- blink LED slow */ #define PHY_LEDCFG_1_LRS 0xC000 /* LED1 Display Link and Receive Status combined */ #define PHY_LEDCFG_1_LAS 0xD000 /* LED1 Display Link and Activity Status combined */ #define PHY_LEDCFG_1_DCS 0xE000 /* LED1 Display Duplex and Collision Status combined */ /* * Digital config register 26 */ #define PHY_DCFG_SH_SER 0x0200 /* Show Symbol Error */ #define PHY_DCFG_DRV_STR 0x0800 /* MII Drive Strength */ /* * Transmit control register 30 */ #define PHY_TXCTL_RT3_0 0x0000 /* Port Rise Time Control: 00 = 3.0 ns (default = TXSLEW<1:0> pins) */ #define PHY_TXCTL_RT3_4 0x0400 /* Port Rise Time Control: 01 = 3.4 ns */ #define PHY_TXCTL_RT3_9 0x0800 /* Port Rise Time Control: 10 = 3.9 ns */ #define PHY_TXCTL_RT4_4 0x0C00 /* Port Rise Time Control: 11 = 4.4 ns */ #define PHY_TXCTL_LWPWR 0x1000 /* 1 = Forces the transmitter into low power mode */ #endif /////