/* * LAN8710A PHY transceiver registers. * * Copyright (C) Elvees (www.multicore.ru) * * This file is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. * * You can redistribute this file and/or modify it under the terms of the GNU * General Public License (GPL) as published by the Free Software Foundation; * either version 2 of the License, or (at your discretion) any later version. * See the accompanying file "COPYING.txt" for more details. * */ #define PHY_CTL 0 /* Basic Control */ #define PHY_STS 1 /* Basic Status */ #define PHY_ID1 2 /* PHY Identifier I */ #define PHY_ID2 3 /* PHY Identifier II */ #define PHY_ADVRT 4 /* Auto-Negotiation Advertisement */ #define PHY_RMT_ADVRT 5 /* Auto-Negotiation Link Partner Ability */ #define PHY_ANE 6 /* Auto-Negotiation Expansion */ //#define PHY_ANNP 7 /* Auto-Negotiation Next Page */ //#define PHY_LPNPA 8 /* Link Partner Next Page Ability */ #define PHY_MCS 17 /* Mode Control/Status */ #define PHY_SPMD 18 /* Special Modes */ #define PHY_ERCNT 26 /* Symbol Error Counter */ #define PHY_CSIND 27 /* Control/Status Indication */ #define PHY_ISRC 29 /* Interrupt Source */ #define PHY_IMSK 30 /* Interrupt Mask */ #define PHY_SCS 31 /* Special Control/Status */ /* * Basic Control Register 0x00 */ #define PHY_CTL_COLTST 0x0080 /* collision test enable */ #define PHY_CTL_DPLX 0x0100 /* full duplex */ #define PHY_CTL_ANEG_RST 0x0200 /* write 1 to restart autoneg */ #define PHY_CTL_MII_DIS 0x0400 /* MII interface disable */ #define PHY_CTL_PDN 0x0800 /* powerdown enable */ #define PHY_CTL_ANEG_EN 0x1000 /* auto-negotiation enable */ #define PHY_CTL_SPEED_100 0x2000 /* select 100 Mbps speed */ #define PHY_CTL_LPBK 0x4000 /* loopback enable */ #define PHY_CTL_RST 0x8000 /* reset, bit self cleared */ #define PHY_CTL_BITS "\20\10coltst"\ "\11dplx\12aneg-rst\13mii-dis\14pdn\15aneg-en\16speed100\17lpbk\20rst" /* * Basic Status register 0x01 */ #define PHY_STS_EXREG 0x0001 /* extended regs enabled */ #define PHY_STS_JAB 0x0002 /* jabber detected */ #define PHY_STS_LINK 0x0004 /* link valid */ #define PHY_STS_CAP_ANEG 0x0008 /* auto-negotiation available */ #define PHY_STS_REM_FLT 0x0010 /* remote fault detected */ #define PHY_STS_ANEG_CMPL 0x0020 /* auto-negotiation complete */ #define PHY_EXT_STATUS 0x0100 /* extended status in register 15 */ #define PHY_STS_CAP_100_HDX 0x0200 /* can do 100Base-T2 half duplex */ #define PHY_STS_CAP_100_FDX 0x0400 /* can do 100Base-T2 full duplex */ #define PHY_STS_CAP_10_HDX 0x0800 /* 10Base-T half duplex */ #define PHY_STS_CAP_10_FDX 0x1000 /* 10Base-T full duplex */ #define PHY_STS_CAP_100X_HDX 0x2000 /* can do 100Base-TX half duplex */ #define PHY_STS_CAP_100X_FDX 0x4000 /* can do 100Base-TX full duplex */ #define PHY_STS_CAP_100T4_FDX 0x8000 /* can do 100Base-T4 */ #define PHY_STS_BITS "\20"\ "\1exreg\2jab\3link\4cap-aneg\5rem-flt\6aneg-cmpl\9ext-stat"\ "\10hdx100T2\11fdx100T2\12hdx10T\13fdx10T\14hdx100TX\15fdx100TX\16T4-100" /* * ID1-ID2 registers */ #define PHY_ID1_NUMB 0x0007 #define PHY_ID_MASK 0xfffffff0 #define PHY_ID2_NUMB 0x0007C0F0 /* * Auto negotiation advertisement, * Auto negotiation remote end capability 0x04 */ #define PHY_ADVRT_CSMA 0x0001 /* capable of 802.3 CSMA operation */ #define PHY_ADVRT_10 0x0020 /* can do 10Base-T */ #define PHY_ADVRT_10_FDX 0x0040 /* can do 10Base-T full duplex */ #define PHY_ADVRT_100 0x0080 /* can do 100Base-TX */ #define PHY_ADVRT_100_FDX 0x0100 /* can do 100Base-TX full duplex */ //#define PHY_ADVRT_100_T4 0x0200 /* can do 100Base-T4 */ //#define PHY_ADVRT_PAUSE 0x0400 /* pause function supported */ #define PHY_ADVRT_RF 0x2000 /* remote fault */ // Pause Operation #define PHY_SYMM_PAUSE 0x0400 /* Symmetric Pause */ #define PHY_ASYMM_PAUSE 0x0800 /* Asymmetric Pause toward link partner */ #define PHY_SMASM_PAUSE 0x0C00 /* Symmetric and Asymmetric pause toward local device */ #define PHY_ADVRT_BITS "\20"\ "\1csma\5t10\6fdx-t10\7tx100\8fdx-tx100\13rf" /* * Auto negotiation link partner ability register 0x05 */ #define PHY_ANLP_CSMA 0x0001 /* capable of 802.3 CSMA operation */ #define PHY_ANLP_10T 0x0020 /* capable 10BASE-T */ #define PHY_ANLP_10TFDX 0x0040 /* capable 10BASE-T full duplex */ #define PHY_ANLP_100TX 0x0080 /* capable 100BASE-TX */ #define PHY_ANLP_100TXFDX 0x0100 /* capable 100Base-TX full duplex */ #define PHY_ANLP_100T4 0x0200 /* capable 100Base-t4 */ #define PHY_ANLP_PAUSE 0x0400 /* Pause supported */ #define PHY_ANLP_RFLT 0x2000 /* Remote fault */ #define PHY_ANLP_ACK 0x4000 /* Acknowledge */ #define PHY_ANLP_NP 0x8000 /* Next Page */ /* * Auto negotiation expansion register 0x06 */ #define PHY_ANEX_ANAB 0x0001 /* Link partner auto-negotiation able */ #define PHY_ANEX_PGRCV 0x0002 /* Page received */ #define PHY_ANEX_NPAB 0x0004 /* Next page able */ #define PHY_ANEX_LPNPAB 0x0008 /* Link partner next page able */ #define PHY_ANEX_PDF 0x0010 /* Parallel detection fault */ /* * Mode Control/Status Register 17 */ #define PHY_MCS_ENERGON 0x0002 #define PHY_MCS_PHYADBP 0x0008 /* disregads PHY address in SMI access write */ #define PHY_MCS_ALTINT 0x0040 /* Alternative int mode */ #define PHY_MCS_FARLOOPBACK 0x0200 /* Force the module to the FAR Loop mode */ #define PHY_MCS_MDPREBP 0x0400 /* Management Data Preamble bypass */ #define PHY_MCS_LOWSQEN 0x0800 /* implies a lower Squelch threshold - more sensitive */ #define PHY_MCS_EDPWRDOWN 0x2000 /* Energy Detect Power-Down is enabled */ /* * Special modes register 18 */ #define PHY_SPMD_RMIIMD 0x4000 /* Rmii mode */ /* * Special contrl/status indications 27 */ #define PHY_CSIND_AMDIXCTRL (1 << 15) /* HP Auto-MDIX control: 1 - disable Auto-MDIX */ #define PHY_CSIND_CH_SELECT (1 << 13) /* Manual Channel Select */ #define PHY_CSIND_SQEOFF (1 << 11) /* Disable the SQE test */ #define PHY_CSIND_XPOL (1 << 4) /* Polarity of the 10Base-T: 0 - Normal; 1 - Reversed */ /* * Interrupt Source register 29 */ #define PHY_ISRC_INT7 (1 << 7) /* Int7 - ENERGYON generated */ #define PHY_ISRC_INT6 (1 << 6) /* Int6 - Auto-Negotiation complete */ #define PHY_ISRC_INT5 (1 << 5) /* Int5 - Remote Fault Detected */ #define PHY_ISRC_INT4 (1 << 4) /* Int4 - Link Down */ #define PHY_ISRC_INT3 (1 << 3) /* Int3 - Auto-Negotiation LP Acknowledge */ #define PHY_ISRC_INT2 (1 << 2) /* Int2 - Parallel Detection Fault */ #define PHY_ISRC_INT1 (1 << 1) /* Int1 - Auto-Negotiation page received */ /* * Interrupt Mask register 30 */ #define PHY_IMSK_INT7 (~(1 << 7)) /* 0 - Mask Int7 - ENERGYON generated */ #define PHY_IMSK_INT6 (~(1 << 6)) /* 0 - Mask Int6 - Auto-Negotiation complete */ #define PHY_IMSK_INT5 (~(1 << 5)) /* 0 - Mask Int5 - Remote Fault Detected */ #define PHY_IMSK_INT4 (~(1 << 4)) /* 0 - Mask Int4 - Link Down */ #define PHY_IMSK_INT3 (~(1 << 3)) /* 0 - Mask Int3 - Auto-Negotiation LP Acknowledge */ #define PHY_IMSK_INT2 (~(1 << 2)) /* 0 - Mask Int2 - Parallel Detection Fault */ #define PHY_IMSK_INT1 (~(1 << 1)) /* 0 - Mask Int1 - Auto-Negotiation page received */ /* * Special control/status register 31 */ #define PHY_SCS_AUTODONE (1 << 12) /* Auto-Negotiation done */ #define PHY_SCS_4B5B_EN (1 << 6) /* 4B/5B enable */ #define PHY_SCS_SCRAMB_DIS (1 << 0) /* Scramble sisable */ #define PHY_SCS_HCDSPD_MSK (7 << 2) /* HCDSPEED mask */ #define PHY_SCS_HCDSPD_10HD (0x001 << 2)/* 10Mbps Half duplex */ #define PHY_SCS_HCDSPD_10FD (0x101 << 2)/* 10Mbps Full duplex */ #define PHY_SCS_HCDSPD_100HD (0x010 << 2) /* 100Base-TX Half duplex */ #define PHY_SCS_HCDSPD_100FD (0x110 << 2) /* 100Base-TX Full duplex */ #define PHY_SCS_GPO20_MSK (7 << 7) /* GPO[2..0] mask */