// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2020
 *
 */

#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
// #include <netdev.h>
#include	<../mach-elvees/include/elvees-periph.h>

void ddr_init(void);

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{

#ifdef CONFIG_INIT_MPORT
	void __iomem *regs;

	regs	=	map_physmem(MPORT_BASE, MPORT_SIZE, MAP_NOCACHE);
	writel(0xb000f8, regs+CSCON0_OFF);
	////	init SDRAM
	writel(0x06180030, regs+SDRCON_OFF);
	writel(0x00740111, regs+SDRTMR_OFF);
	writel(0x40, regs+SDRCSR_OFF);
	writel(0x01, regs+SDRCSR_OFF);
#endif


	/* Sdram is setup by assembler code */
	/* If memory could be changed, we should return the true value here */
	gd->ram_size = MEM_SIZE * 1024 * 1024;

	ddr_init();

	return 0;
}

void ddr_init(void)
{
#ifdef CONFIG_INIT_DDR
	void __iomem *regs_ddr0;
	void __iomem *regs_ddr1;

	regs_ddr0	=	map_physmem(DDR_PORT0_BASE, DDR_PORT_SIZE, MAP_NOCACHE);
	regs_ddr1	=	map_physmem(DDR_PORT1_BASE, DDR_PORT_SIZE, MAP_NOCACHE);

	writel(0x04001020, regs_ddr0+DDR_CON_OFF);
	writel(0x04001020, regs_ddr1+DDR_CON_OFF);

	writel(DDR_TMR, regs_ddr0+DDR_TMR_OFF);
	writel(DDR_TMR, regs_ddr1+DDR_TMR_OFF);

	writel(0x40fc, regs_ddr0+DDR_BAR_OFF);
	writel(0x10fc, regs_ddr1+DDR_BAR_OFF);

	writel(0, regs_ddr0+DDR_MOD_OFF);
	writel(0, regs_ddr1+DDR_MOD_OFF);

	writel(0x40, regs_ddr0+DDR_CSR_OFF);
	writel(0x40, regs_ddr1+DDR_CSR_OFF);

	writel(0x01, regs_ddr0+DDR_CSR_OFF);
	writel(0x01, regs_ddr1+DDR_CSR_OFF);

	writel(0x20, regs_ddr0+DDR_CSR_OFF);
	writel(0x20, regs_ddr1+DDR_CSR_OFF);
#endif

}

int checkboard(void)
{
	u32 proc_id;
	u32 config1;

	proc_id = read_c0_prid();
	printf("Board: Elvees mips CPU: ");
	switch (proc_id) {
	case 0x00018000:
		printf("4Kc");
		break;
	case 0x00018400:
		printf("4KEcR1");
		break;
	case 0x00019000:
		printf("4KEc");
		break;
	case 0x00019300:
		config1 = read_c0_config1();
		if (config1 & 1)
			printf("24Kf");
		else
			printf("24Kc");
		break;
	case 0x00019500:
		printf("34Kf");
		break;
	case 0x00000400:
		printf("R4000");
		break;
	case 0x00018100:
		config1 = read_c0_config1();
		if (config1 & 1)
			printf("5Kf");
		else
			printf("5Kc");
		break;
	case 0x000182a0:
		printf("20Kc");
		break;

	default:
		printf("unknown");
	}
	printf(" proc_id=0x%x\n", proc_id);

	return 0;
}

int misc_init_r(void)
{
	//ddr_init();
	set_io_port_base(0);
	return 0;
}
/*
int board_eth_init(bd_t *bis)
{
	return ne2k_register();
}
*/
/*
int
board_run_command(const char* cmdline)
{
	return	1;
}
*/


void flush_cache(unsigned long start, unsigned long size)
{
}

int dcache_status(void)
{
	unsigned int cca = read_c0_config() & CONF_CM_CMASK;
	return cca != CONF_CM_UNCACHED;
}

void dcache_enable(void)
{
	puts("Not supported!\n");
}

void dcache_disable(void)
{
	/* change CCA to uncached */
	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);

	/* ensure the pipeline doesn't contain now-invalid instructions */
	instruction_hazard_barrier();
}

void mips_cache_probe(void)
{
#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
	unsigned long conf1, il, dl;

	conf1 = read_c0_config1();

	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;

	gd->arch.l1i_line_size = il ? (2 << il) : 0;
	gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
#endif
	//probe_l2();
}