/* Memory sub-system initialization code */

#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>

	.text
	.set noreorder
	.set mips32

	.globl	lowlevel_init
lowlevel_init:

	/*
	 * Step 2) Establish Status Register
	 * (set BEV, clear ERL, clear EXL, clear IE)
	 */
	li	t1, 0x00400000
	mtc0	t1, CP0_STATUS

	/*
	 * Step 3) Establish CP0 Config0
	 * (set K0=3)
	 */
	li	t1, 0x00000003
	mtc0	t1, CP0_CONFIG

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
#	li	t1, 0x00800000
#	mtc0	t1, CP0_CAUSE

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_WIRED
	nop

#######################################################
#	TODO!!!
		/*  init system PLL & clocks */
	la     v1, ELVEES_SYSTEM
	move   v0, zero
	sw     v0, 0x7c(v1)						/*	#CR_PLL1. ACC is OFF */

    ori    v0, (0x80 + (CONFIG_SYS_MHZ / 5))
#ifdef MPORT_FRQ
    ori    v0, ((0x80 + (MPORT_FRQ / 5)) << 8)
#endif

#ifdef DSP_FRQ
    li     t1, ((0x80 + (DSP_FRQ / 5)) << 16)
    or     v0, v0, t1
#endif

#ifdef DDR_FRQ
    li     t1, ((0x80 + (DDR_FRQ / 5)) << 24)
    or     v0, v0, t1
#endif
	sw     v0, 0(v1)

	#li     v0, 0xffffffff
	li     v0, 0x007fffff
	sw     v0, 4(v1)
#######################################################


	jr	ra
	nop