/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * common register definitions
 */

#ifndef	MACH_ELVEES_REGS_H
#define MACH_ELVEES_REGS_H


#define	ELVEES_BASE	0x182F0000


#define	MPORT_BASE	(ELVEES_BASE+0x1000)
//#define	MC30SF6_MPORT_SIZE	0x30
//#define	NVCOM02_MPORT_SIZE	0x20

#define	CSCON0_OFF	0
#define	CSCON1_OFF	0x04
#define	CSCON2_OFF	0x08
#define	CSCON3_OFF	0x0c
#define CSCON4_OFF	0x10

#define SDRCON_OFF	0x14
#define SDRTMR_OFF	0x18
#define SDRCSR_OFF	0x1c



#define	DDR_BAR_OFF	0x10
#define	DDR_CON_OFF	0x14
#define	DDR_TMR_OFF	0x18
#define	DDR_CSR_OFF	0x1C
#define	DDR_MOD_OFF	0x20
#define	DDR_EXT_OFF	0x24
#define	DDR_ERR_OFF	0x28

#endif